IP & Products


Mulberry1 Solutions
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The MULBERRIX DURO family are FPGA Mezzanine Card (FMC) modules, electrical compatible with FMC/FMC+ Vita 57.4 interface standard

MULBERRIX DURO-100G-SFP

  • FMC+ Compatible ( Vita 57)
  • 2 ports SFP 100G
  • 8 Ports SFP 1G-25G
  • 16 SFP bi-color LEDS on cage
  • The LOS, TX_Fault and MDL_Det
  • USB3 high speed comm Channel
  • On Board low jitter CLK
  • 50 IO expansion signals
  • Two 50mil headers 50pin and 26pin
  • DURO-HMI – seamless connect HMI

MULBERRIX DURO-100G-SFP

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Powerful USB3 type-C Interface providing high speed interface from the FPGA utilizing high speed . parallel bus. In addition, JTAG, SPI and UART can be emulated via the USB3 interface, including , interrupt towards the FPGA. Two high speed UARTs via independed USB2 Micro connector- providing is very useful interface .
for the FPGA cards, especially for the new FPGA cards lake of having UART interfaces .
68 expansion signals from the FMC connecter can be access via 100mil headers for general use .

MULBERRIX DURO-EXP

  • FMC+ Compatible ( Vita 57)
  • USB3 high speed comm Channel with SPI, UART and parallel
  • Additional UART via USB2
  • IO Expander
  • 68 IO expansion signals
  • 100 Mil Headers
  • Voltage levels shifter
  • 50 IO expansion signals

MULBERRIX DURO-EXP

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Our special software tool that automatically generates CPU Peripheral components for FPGA design. This fully automated tool reduces the implementation and testing time of register files from hundreds of hours to a fraction of that time .

MULBERRIX Dulce-Regs

  • Fast tool to create CPU interface files
  • Register
  • Counters
  • AXI-Lite, AVL, SPI, I2C more
  • Seamless integrated withing Vivado and NIOS block design
  • Seamless integrated withing QSYS

MULBERRIX Dulce-Regs

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Our special software tool that automatically generates CPU Peripheral components for FPGA design. This fully automated tool reduces the implementation and testing time of register files from hundreds of hours to a fraction of that time .

MULBERRIX Dulce-Regs

  • Fast tool to create CPU interface files
  • Register
  • Counters
  • AXI-Lite, AVL, SPI, I2C more
  • Seamless integrated withing Vivado and NIOS block design
  • Seamless integrated withing QSYS

MULBERRIX Dulce-Regs

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The MULBERRIX Dulce-sDMA High-Bandwidth DMA between Memory-Mapped and Stream interfaces

MULBERRIX Dulce-sDMA

  • Supports AXIs or AvalonS interfaces
  • Independent Write & Read (for AXI Interface)
  • Simple Control and Status interface for the User
  • Configurable Address (32/64) and Data width (32/64/128/256/512/1024)
  • Supports different widths between the Memory-Mapped and Streaming
  • Ratios – 1/1, 1/2, 1/4, 2/1, 4/1
  • Configurable Max Burst
  • Supports Stopping the DMA (terminates the last transaction gracefully)
  • Supports Holding the DMA

MULBERRIX Dulce-sDMA

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